MIPS single clock cycle processor in VHDL

This project was basically to implement a MIPS single clock cycle processor. It is slightly different from standard MIPS processor. The processor in this project consists of 8-bit registers and therefore it’s an 8-bit processor while the standard MIPS processor is a 32-bit processor. In this processor only 8 registers are implemented but in standard MIPS processor there are 32 registers. But the common feature between these two processors is both process 32-bit instructions.



When implementing, we were given main components of the processor. To make it simple what I did was, I printed the RTL Schematic diagram of all the components separately and pasted them in a large A3 paper. Then I connected pins one by one in the diagram using a pencil in A3 paper according to figure in the project handout. At the same time I did the port mapping in the Xilinx project to avoid any careless mistakes that we do as humans.

After completing the port mapping, syntaxes were checked by the ‘Check Syntax’ function in Xilinx. Then again the RTL Schematic diagram was generated to double check the answers. It was similar to the diagram that I had in the A3 paper and no errors found in that. Another key thing that I learned from this project is to assign FPGA board pins to the project input and outputs. It is done creating a User Constraint File (UCF).

After downloading the program into the board, some times we noticed the program doesn’t work correctly due to a loose connection of the cable. To overcome this problem one of the completed project was downloaded and verified if the cable works properly.

Another important point that I learned is how to generate memories by Xilinx Core. The difference between the generated memory and the VHDL based memory is another important factor that we understood. We also learned how to slow down the clock speed of the oscillator using a component in VHDL.

After finishing the part A when we tried to do part B we got an unresolvable error while trying to implement it. That’s due to a file confliction with the generated memory files in part A of the project. We overcame with that problem by cleaning the project files.

The overall project was successful. It is because we started it with a good preparation and the printed schematic diagram of components and connecting them by hand made the project a lot easy visualize and code. When doing complex projects like this, it is always better to have a hard copy of diagrams so that it is easy to visualize and will help a lot to make the coding easy. Not only that, it will save heaps of our precious time.